When placed at a position to concentrate lines of an access network and connect them to a core network, a packet transfer processing apparatus such as a router or switch performs inbound processing of receiving a packet from the access network side where a user apparatus is connected and outbound processing of transmitting a packet to the access network side.
As shown in FIG. 8, a packet transfer processing apparatus 50 includes a register file 51, a selector 52, a data write unit 53, a packet buffer BUF, and a data read unit 54 as main functional units used for inbound processing.
The register file 51 is provided for each line from a first network NW1 formed from an access network or the like, and has a function of receiving a packet from each line and holding it in the internal register of its own.
The selector 52 has a function of selecting a packet read out of the register file 51.
The data write unit 53 has a function of inputting a packet selected by the selector 52 to a write port PW of the packet buffer BUF.
The packet buffer BUF is formed from a dual port type SRAM including the write port PW and a read port PR, and has a function of writing a packet input from the data write unit 53 to the write port PW in a storage area designated by write address information out of the SRAM in accordance with a write instruction, and a function of reading out a packet from a storage area designated by read address information out of the SRAM and outputting the packet from the read port PR to the data read unit 54 in accordance with a read instruction.
The data read unit 54 has a function of transmitting a packet read out of the packet buffer BUF to a second network NW2.
As shown in FIG. 8, the packet transfer processing apparatus 50 also includes a FIFO management unit 61, a read and selection control unit 62, a write control unit 63, a read control unit 64, and an address control unit 65 as main functional units used for access control of the packet buffer BUF in the inbound processing.
The FIFO management unit 61 has a function of managing the amount of packets and address information written in each register file 51.
The read and selection control unit 62 has a function of instructing the register file 51 to read out a packet stored in the register file 51 in accordance with the amount of packets and address information output from the FIFO management unit 61 and instructing the selector 52 to do packet selection including discard, and a function of outputting the address information of a packet selected by the selector 52 and a write instruction to the write control unit 63.
The write control unit 63 has a function of outputting the address information output from the read and selection control unit 62 to the address control unit 65, and a function of outputting the write instruction output from the read and selection control unit 62 to the packet buffer BUF.
The read control unit 64 has a function of outputting the address information of a packet to be read out of the packet buffer BUF to the address control unit 65, and a function of outputting the read instruction of the packet to the packet buffer BUF.
The address control unit 65 has a function of outputting address information output from the write control unit 63 to the packet buffer BUF as the write address of a packet to be written in the packet buffer BUF, and a function of outputting address information output from the read control unit 64 to the packet buffer BUF as the read address of a packet to be read out of the packet buffer BUF.
Hence, in the conventional packet transfer processing apparatus 50 shown in FIG. 8, when writing a packet received from the first network NW1 in the packet buffer BUF, based on the amount of packets in each register file 51 managed by the FIFO management unit 61, the read and selection control unit 62 selects a packet to be written. Based on a write instruction and address information representing the storage location of the packet, which are output from the read and selection control unit 62, the write control unit 63 and the address control unit 65 execute access control of the packet buffer BUF, thereby writing the packet.
When reading out a packet from the packet buffer BUF and transmitting it to the second network NW2, based on a read instruction and address information representing the storage location of a packet to be read out, which are output from the read control unit 64, the read control unit 64 and the address control unit 65 execute access control of the packet buffer BUF, thereby reading out the packet.